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MC74F194 4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTER
The MC74F194 is a high-speed 4-bit bidirectional universal shift register. As a high-speed multifunctional, sequential building block, it is useful in a wide variety of applications. It may be used in serial-serial, shift left, shift right, serial-parallel, parallel-serial, and parallel-parallel data register transfers. The F194 is similar in operation to the S195 universal shift register, with added features of shift left without external connections and hold (do nothing) modes of operation.
4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTER
FASTTM SCHOTTKY TTL
* * * *
Typical Shift Frequency of 150 MHz Asynchronous Master Reset Hold (Do Nothing) Mode Fully Synchronous Serial or Parallel Data Transfers
16 1
FUNCTIONAL DESCRIPTION The F194 contains four edge-triggered D flip-flops and the necessary interstage logic to synchronously perform shift right, shift left, parallel load and hold operations. Signals applied to the Select (S0, S1) inputs determine the type of operation, as shown in the Function Table. Signals on the Select, Parallel data (P0 - P3) and Serial data (DSR, DSL) inputs can change when the clock is in either state, provided only that the recommended setup and hold times, with respect to the clock rising edge, are observed. A LOW signal on Master Reset (MR) overrides all other inputs and forces the outputs LOW. CONNECTION DIAGRAM
VCC 16 Q0 15 Q1 14 Q2 13 Q3 12 CP 11 S1 10 S0 9
J SUFFIX CERAMIC CASE 620-09
16 1
N SUFFIX PLASTIC CASE 648-08
16 1
D SUFFIX SOIC CASE 751B-03
ORDERING INFORMATION
MC74FXXXJ MC74FXXXN MC74FXXXD Ceramic Plastic SOIC
1 MR
2 DSR
3 P0
4 P1
5 P2
6 P3
8 7 DSL GND
FUNCTION TABLE
Operating Mode Reset Hold Shift Left Shift Right Parallel Load Inputs MR L H H H H H H S1 X I h h I I h S0 X I I I h h h DSR X X X X I h X DSL X X I h X X X Pn X X X X X X pn Q0 L q0 q1 q1 L H p0 Outputs Q1 L q1 q2 q2 q0 q0 p1 Q2 L q2 q3 q3 q1 q1 p2 Q3 L q3 L H q2 q2 p3 1 15 14 13 12
LOGIC SYMBOL
11 10 9 CP S1 S0 DSR MR P0 Q0 P1 Q1 P2 Q2 P3 DSL Q3
2 3 4 5 6 7
I = LOW voltage level one setup time prior to the LOW-to-HIGH clock transition. h = HIGH voltage level one setup time prior to the LOW-to-HIGH clock transition. pn, qn = Lower case letters indicate the state of the referenced input or output one setup time prior to the LOW-to-HIGH clock transition. H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial
VCC = PIN 16 GND = PIN 8
FAST AND LS TTL DATA 4-101
MC74F194
LOGIC DIAGRAM
P0 S1 S0 P1 P2 P3
DSR
DSR
S
Q0
S
Q1
S
Q2
S
Q3
CP R CLEAR CP MR Q0
CP R CLEAR
CP R CLEAR
CP R CLEAR
Q1
Q2
Q3
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
GUARANTEED OPERATING RANGES
Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current -- High Output Current -- Low Parameter 74 74 74 74 Min 4.5 0 Typ 5.0 25 Max 5.5 70 - 1.0 20 Unit V C mA mA
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits Symbol VIH VIL VIK VOH VOL IIH IIL IOS Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage 74 Output HIGH Voltage 74 Output LOW Voltage Input HIGH Current 100 Input LOW Current Output Short Circuit Current (Note 2) - 60 - 0.6 -150 2.7 3.4 0.35 0.5 20 V V A A mA mA 2.5 3.4 Min 2.0 0.8 - 1.2 Typ Max Unit V V V V Test Conditions Guaranteed Input HIGH Voltage Guaranteed Input LOW Voltage IIN = -18 mA IOH = -1.0 mA IOH = -1.0 mA IOL = 20 mA VIN = 2.7 V VIN = 7.0 V VIN = 0.5 V VOUT = 0 V Sn, MR, DSR, DSL = 4.5 V Pn = Gnd, CP = VCC = MIN VCC = 4.5 V VCC = 4.75 V VCC = MIN VCC = MAX VCC = MAX VCC = MAX
ICC
Power Supply Current
33
46
mA
VCC = MAX
NOTES: 1. For conditions such as MIN or MAX, use the appropriate value specified under guaranteed operating ranges. 2. Not more than one output should be shorted at a time, nor for more than 1 second.
FAST AND LS TTL DATA 4-102
MC74F194
AC CHARACTERISTICS
74F TA = +25C VCC = +5.0 V CL = 50 pF Symbol fmax tPLH tPHL tPHL Parameter Maximum Shift Frequency Propagation Delay CP to Qn Propagation Delay MR to Qn Min 105 3.0 3.5 4.5 7.0 7.5 12 Max 74F TA = 0 to +70C VCC = 5.0 V 10% CL = 50 pF Min 90 3.5 3.5 4.5 8.0 8.0 14 Max Unit MHz ns ns
AC OPERATING REQUIREMENTS
74F TA = +25C VCC = +5.0 V Symbol ts(H) ts(L) th(H) th(L) ts(H) ts(L) th(H) th(L) tw(H) tw(L) trec Parameter Set up Time, HIGH or LOW Pn or DSR or DSL to CP Hold Time, HIGH or LOW Pn or DSR or DSL to CP Set up Time, HIGH or LOW Sn to CP Hold Time, HIGH or LOW Sn to CP CP Pulse Width HIGH MR Pulse Width LOW Recovery Time MR to CP Min 4.0 4.0 0 0 8.0 8.0 0 0 5.0 5.0 7.0 Max 74F TA = 0 to +70C VCC = 5.0 V 10% Min 4.0 4.0 ns 1.0 1.0 9.0 8.0 ns 0 0 5.5 5.0 8.0 ns ns ns Max Unit
FAST AND LS TTL DATA 4-103

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